High density record and reproduce system



June 30, 1970 K. A, NoRRls 3,518,648 I y HIGH DENSITY RECORD ANDREPRODUCE SYSTEM Filed Nov. 7, 1966 4 Sheets-Shed'l .'5

@W6/@MMIV 0 n 0 0 fi ffm/ffm mmm ff i mmf mm1 I 4:7 ffm J/n @www @afm/famm Affi? MW/7M;

4f @ma/mmm 0 0 0 0 0 afa/AWM- .fx/[iwf June 30, 1970 K. A. NoRRls3,518,648

HIGH DENSITY RECORD AND REPRODUCE SYSTEM Filed Nov. 'L 1966 4Sheets-Sheet L f7 ff /f' L/ 7 227 Fmr iii fm/M4 mf 77 MM I affirm! iWA/fn?? ff United States Patent O 3,518,648 HIGH DENSITY RECORD ANDREPRODUCE SYSTEM Kermit A. Norris, Azusa, Calif., assignor, by mesneassignments, to Subscription Television, Inc., New York, N.Y., acorporation of Delaware Filed Nov. 7, 1966, Ser. No. 592,458 Int. Cl.Gllb /00, 5/02, 5/06 U.S. Cl. S40-174.1 Z1 Claims ABSTRACT OF THEDISCLOSURE High density methods and apparatus for storing and recoveringdigital data on a magnetic medium are disclosed. A continuous signalrepresents binary data by level crossings, or signal transitions, at bitcell boundaries with the presence or absence of an additional signaltransition respectively defining one or the other of two bit types. Thedata-containing continuous signal is linearily, or nonsaturably, storedon a magnetic medium in the form, of continuous flux variations. Duringdata recovery a transducer responds to the continuous ux variations soas to restore them to a data-representing signal. The restored signal isdelayed by a one-bit cell delay interval. Both the delayed andnondelayed signals are compared with each other free of any clocksignal, and signal similarities or signal differences. respectively, areemployed for restoring the original binary data.

BACKGROUND` OF THE INVENTION 1Field of the invention This inventionrelates in general to method and apparatus for improving the packingdensity of digital data on a magnetic storage medium. More particularly,this invention relates to new and improved data formats includingdigital to carrier to digital conversions lwhich are applicable tomagnetic storage mediums such as magnetic tapes, magnetic drums, diskiiles, and the like.

Description of the prior art Storage on a magnetic surface has beenunder intensive study for many years. A thin layer of magnetic materialis deposited on a surface and a magnetic head is employed to magnetizeareas or spots on the magnetic layer. The magnetic flux pattern at suchareas or spots indicates whether a zero or a one digit is `stored in aparticular area of the layer. Relative motion between the magnetic layerof the surface and the same or a similar head is employed to recover thedata in the form of induced voltages resulting from changing flux linescutting across a gap in the head. The induced voltages are indicative ofthe value of the data stored on the areas or spots provided that the bitpositions may, during subsequent recovery operations, be ascertained.

During the past decade numerous improvements in the quality of magneticcoatings and the characteristics of magnetic heads have been developed.In spite of these many improvements, the packing density of binaryinformation on a magnetic surface has not shown a correspondingincrease; but, rather, has increased very little. For example, inchapter 7 of Digital Computer Components and Circuits by R. K. Richards,pages 314 through 353, a thorough discussion of the then presently knowndigital data handling techniques, resulted in recorded pulse density ofapproximately 1,150 bits per inch for contact type heads and magnetictape. The state of the art, prior to the advent of this invention andduring the past decade has only managed to increase the bit density toapproximately 2,730 bits per inch, per track,

ice

in a highly specialized piece of equipment for spacecraft use. Forexample, in the Aug. 24, 1964 issue of Electronics, arecorder-reproducer for the Gemini project achieves a packing density of2,730 bits per linear inch perktrack. This packing density is thererepresented as being nearly twice the highest packing density availablein standard magnetic recorders, and is further represented as being twoand one-half times the highest packing density which is available intelemetry recorders.

The foregoing prior art systems for storing information on a magneticsurface may be classed broadly as falling within one of two typicalapproaches. These two approaches involve either a recorded clock or aderived clock. In the prior art approach, utilizing a recorded clock,the clock source 'which is available for clocking digital data during arecord operation, is itself recorded on a separate track on the magneticsurface. This clock track may then be recovered along with the data in asubsequent data recovery operation. This recorded clock approach allowseach pulse of the reference clock to establish the bit cell period forthe data stored in its separate track on the magnetic surface.

In the derived clock technique, timing is provided in the form of aphase-locked oscillator which is triggered by manipulation of the storeddata itself following recovery of such stored data from the magneticsurface of a tape. As another altemative to this second derived clockapproach of the prior arts attempt to eliminate a recorded clockreference, a series of unique bits are stored in the data track prior tothe first information bit of data to be stored. These unique bits, whenrecovered, are used to trigger an external timing source such as aphase-locked oscillator. Although not strictly a clock reference in thesense described above for the recorded clock approach, this second priorart approach is nevertheless dependent upon a timing mechanism of onesort or another. High packing densities are hindered because the datamust be programmed before it is stored on the tape. Thus, the data isnormally divided into blocks and the unique bits are recorded betweendata blocks so that the external clock can continually be up-dated andkept in synchronism -with the data locations. Much data recording spaceis lost. The programming of data for write operations is a costly andcomplex approach. Further, in spite of this expense and complexity, muchdata is lost from blocks between the unique bits because the absence ofa bit due to dirt, head displacement, etc. fwill be represented as aphase displacement in the reference signal and erroneous readings duringthe remainder of the data block occur.

In either the recorded clock or derived clock approaches of the priorart, a recovery operation of stored data must rely on the timing sourcefor establishing bit cell locations. These bit cell intervals allow someform of integration, rectification, or peak detection operation to takeplace on the signals recovered from the magnetic medium so that thedigital levels there represented are derived and are available fordigital data utilization circuits.

SUMMARY OF THE INVENTION I have discovered that the reliance on andnecessity for a clock reference to maintain time relationship of thedata locations is one of several critical factors that has seriouslyhindered high packing density of prior art approaches. RegardlessIwhether the reference clock is recorded on the magnetic surface itself,or whether it is derived from the stored data, this reference makesrecovery of the data difficult, and leads to erroneous readings becausca missing bit of data may be interpreted as a phase displacement of theclock reference signal and all further readings will be erroneous.Furthermore,

3 the prior art techniques of data recovery operations includingrectification, integration, peak detection, and the like, are alldependent upon a clocked reference of some sort and thus suffer the samehigh density limitations mentioned hereinbefore.

The foregoing disadvantages of the prior art are avoided in accordancewith the principles of this invention wherein a new and unique formatand new and unique methods are employed to provide storage on a magneticsurface. Higher packing densities than were heretofore thought possibleare readily provided. At least one, and in one embodiment, two binarybits per cycle of available bandwidth of the storage system is possible.The bandwidth of any storage and recovery system for a magnetic surfaceis a function of the magnetic material, relative speed of movement ofthe surface past the read and write heads, the head design andassociated material, and other parameters of the system itself. Forexample, the state of the art recorders today present a bandwidth ofapproximately 15,000 cycles per second at a signal to noise ratio ofapproximately 18 to 20 decibals. In accordance with the techniques ofthis invention, I have stored and recovered with extremely low errorrates, digital data having packing densities of 30,000 bits per inch pertrack on a magnetic surface. It should be understood that with thetechniques of this invention, the packing density is limited only by thebandwidth of the storage and recovery system and such bandwidth isconstantly improvin-g. Reliance on any timing reference is eliminated inaccordance with the priciples of my invention. Also eliminated are clockdependent operations such as integration, rectification, peak detectionand the like previously required for data recovery. It is theelimination of these critical factors which allows improvement by amagnitude of at least ten over all known prior art techniques.

In accordance with the principles of my invention, digital data, ofeither NRZ or RZ type wherein data is represented by discrete levels, isconverted by a format control into a continuous signal which containsthe digital data in the form of frequency, or phase, variations thereof.This modulated signal is stored by conventional means on a conventionalmagnetic medium, and conventional means are employed to recover thismodulated signal. Once recovered it is applied to means for delaying theinformation signal a fixed integer amount other than Zero which integeramount is equal to, or is a multiple of, the period7 of duration, of thebit cells of the recorded digital data. Means are provided for comparingthe delayed signal with the recovered signal. The output of thiscomparison circuit mixes the delayed and non-delayed signals andrestores phase variations therein to the original digital data format.

BRIEF DESCRIPTION OF THE DRAWING The foregoing and other objects andfeatures of this invention may more readily be appreciated when taken inconjunction with the following description of the figures in which:

FIG. 1 is a block diagram of a high packing density record and reproducesystem in accordance` with the principles of this invention.

FIG. 1A is a chart of pulse and wave forms useful in promoting a clearunderstanding of the system of FIG. 1.

FIG. 2 is a combined block diagram and circuit schematic of the highpacking density system of this invention.

FIG. 2A is a chart of pulse and wave forms useful in promoting a clearunderstanding of FIG. 2.

lFIG. 3 is a combined block and circuit schematic diagram of a systemhaving at least twice the bit density rate of the system of FIG. l inaccordance with principles of this invention;

FIG. 3A is a chart of pulse and wave forms useful in promoting a clearunderstanding of FIG. 3; and

FIG. 4 is a circuit schematic of one suitable filter for FIGS. 2 and 3.

Turning now to the drawing, FIG. 1 depicts a record channel 20 and areproduce channel 50 for respectively recording and reproducing data ona magnetic surface 30. This magnetic surface 30 may be any magneticcoating such as oxide coatings utilized on storage members includingtape, drums, disk files or the like.

In accordance with the principles of this invention, a source 21supplies digital data having at least two discrete levels. Such digitaldata may, for example, be nonreturn to zero data (NRZ) or return to zero(RZ) data. Thus, for purposes of example only, digital Vdata from source21 may be non-return to zero change (NRZC) format as shown in row 1 ofFIG. 1A. In this digital format, data is represented by two distinctlevels wherein a one is represented by one level and a zero isrepresented by a second level.

In FIG. 1A pulse wave forms are identified by encircled numbers. In FIG.1 the wave forms of FIG. 1A are identified as to location by theseencircled numbers. Thus, NRZC data is emitted from source 21, FIG. l, asshown by the encircled number.

A clock source 22 applies a train of pulses to the format converter, orencoder, 25, which clock signal 32 is shown in the second row of FIG.1A. It should be understood that a clock source such as clock source 22is customarily available in all systems for recording digital data. Inaccordance with the principles of my invention, the clock signal 32emitted by the clock source 22 serves as a carrier signal. This clocksignal 32 has a frequency selected to make one complete cycle during abit cell location. It may `be any frequency within the systemsa-vailable bandwidth for the embodiment of FIG. 1. Current record andreproduce systems exhibit a bandwidth having signal to noise ratio ofapproximately 30 decibels from zero to l0 kilocycles per second perlinear recording inch. The signal to noise ratio drops to approximately18 or 20 decibels at a frequency of approximately 15,000 cycles persecond per inch. Accordingly, the frequency of the clock signal 32 mayvary for the circuit of FIG. 1 up to approximately 18,000 cycles persecond per inch for current systems, although obviously this inventionis not limited to such frequencies. The digital data pulse train 31 ofsource 21 serves as a modulating signal for the carrier signalrepresented by clock signal 32 of source 22. The output of formatconverter 25 is thus a digital data modulated carrier signal shown .inrow 3 of FIG. 1A as a data modulated signal 35. This data modulatedsignal 35 is referred to as a split-phase-mark (SqbM) signal, in that atransition occurs at the beginning of every lbit period; with a onerepresented by an additional midbit transition; and a Zero 1srepresented by no midbit transition.

The data modulated signal 35 is shown in FIG. 1A substantially as asquare wave but as will be explained in more detail hereinafter inconnection with FIGS. 2 and 2A, such a modulated signal is recorded onthe magnetic surface as a continuous phase modulated wave. The modulatedsignal 35 of FIG. 1A is recorded on surface 30' by any conventionalrecord transducer, or head 27. Typically record head 27 contacts orrides adjacent to a magnetic recording medium 30 and in response tosignals applied thereto induces flux patterns on the magnetic surface.In my lnvention, no attempt is made to establish saturated fluxreversals for ones and zeroes as is so common in the prior art. Rather,the record head 27 records signal 35 on magnetic surface 30 as acontinually varying flux pattern in which the digital information isrepresented by iiux variations corresponding to phase variations in themodulated signal 35.

Relative movement between magnetic surface 30 and a reproducetransducer, or head 57, converts the continually varying flux patternson magnetic surface 30 back to a data modulated signal 35. It should beunderstood that the output wave form from reproduce head 57 contains thedigital data in phase-modulated form and must be restored to a suitabledigital data pulse pattern utilizing at least two discrete levels so asto be readily available for conventional digital utilization circuitry.

Reliance on any exterior or derived clock train, r integration,rectification, or peak detection operations 4which exemplify the priorart, are avoided by my reproduce channel 50. The data modulated signal35 from a reproduce head 57 is applied to a decoder circuit 55 whichincludes a delay circuit 56 and a demodulator 60. It is well known thatmany precise and highly stable delay devices are currently availablehaving wide ranges of delay. Any such conventional delay 56 may beemployed. A delay of one bit cell interval has been chosen for purposesof illustrating my data recovery technique. A fixed one bit cell delayis shown at row 4 of FIG. 1A wherein the delayed data signal 36 appearsone bit cell interval late compared to the appearance of data signal 35.

It should be noted that the phase modulated data signal 35 is, ofnecessity, a random sequence of phase modulated signals. This randomsequence of phase modulated signals is determined by the original, andlikewise random, pattern of ones and zeroes provided by the source ofdigital data 21. Inasmuch as the digital data is contained in modulatedform in the phase modulated signal 35, a delay of one bit cell in delaycircuit 56, in essence, selects one data bit in delayed form as a basisfor a phase comparison with the first digital bit t0 be ascertained. Thephase of the delayed bit when compared with the phase of this first bit,provides a unique method for determining the digital value of the firstbit. For example, if the phases Of the delayed and first bit whencompared are similar, then one discrete digital level and value isrepresented; whereas if the phase of the delayed bit and the first bitto be ascertained are different, the other discrete digital level andvalue is indicated. The employment of this delayed signal thus providesa novel timing reference for recovering the data in the form of adifferential phase detection technique.

A digital data utilization circuit 67, FIG. 1, is connected to theoutput of demodulator 60 for utilizing the NRZC data signal 37, row 5FIG. 1A, which is emitted at the output of demodulator 60. It is readilyapparent that the employment of the delay circuit 56 and demodulator 60has restored the digital data modulated signal 35 to its originaldigital form 31 without any recovery clock source and without utilizingany of the conventional recovery techniques such as differentiation orpeak detection as used by the prior art. Such prior art techniquesinvolve inherent speed and signal-to-noise limitations which heretoforehas prevented the attainment of any packing densities aboveapproximately 5,000 bits per inch under the most closely controlledlaboratory conditions as reported by some costly and highly experimentalunits. I have attained by my invention, a commercially acceptable systemwhich operates over wide ranges of temperature and without costly handselection of components. In my system packing densities as high as30,000 bits per inch with reliability consistently better than one errorin l06 bits of data is readily attainable.

Reference to FIG. 2, which is a more detailed circuit schematic of thesystem of FIG. l, readily depicts the simplicity of the componentsutilized in my invention. In FIG. 2, components which correspond tosubstantially the same components as FIG. 1 are designated by the samenumbers. Thus, the format converter 25 is depicted as receiving twoinputs which are the NRZC digital data signal 31 shown at row A in FIG.2A and the clock signal 32 shown at row B in FIG. 2A. The formatconverter 25 includes a pair of detectors 23, 24 which receive the clocksignal 32. The pair comprises -a trailing edge detector circuit 23 and aleading edge detector circuit 24. These detector circuits are well knownand may be any suitable detector circuit of the prior art. An AND gate26 receives the output emitted from the leading edge detector 24 `andalso receives, as its other input, NRZC data 31 from input source 21.AND gate 26 delivers an output indication to an OR gate 28 when itsinput conditions from the leading edge detector 24 and the NRZC datasource 21 are true. A second input to OR gate 28 is the output from thetrailing edge detector 23. OR gate 28 triggers any standard flip-fioptoggle circuit 29 so that one change of state of flip-flop 29 isgenerated for each input signal it receives from OR gate 28.

Reference to row B of FIG. 2A discloses that the clocking signal 32 hasa leading edge going positive at the center of each bit cell and it hasa trailing edge going from a positive to a zero or negative level at theend of each bit cell. Recordingly, the leading edge of clock signal 32at the middle of the first bit cell is detected by circuit 24 andcoincides with a positive level from the data source 21 at AND gate 26to form a trigger input pulse for fiip-flop 29. Flip-flop V29 changesstate and produces the first pulse in the data modulatedsplit-phase-mark signal 35 as shown in row C of FIG. 2A. The trailingedge detector 23 then detects the end of the bit cell and again pulsesfiip-flops 29 causing another change of state and presenting a negativelevel to the low-pass filter 33 during the second bit cell. Thisoperation just described continues for the remaining ones and zeroes andthe output from fiip-fiop toggle circuit 29 emits the split-phase-markformat shown at row C in FIG. 2A.

The low-pass filter circuit 33 may be any suitable broad band low-passfilter circuit known in the prior art. One such suitable filter isdepicted in FIG. 4 and comprises resistive and capacitive input andoutput sections 14 and 15 interconnected by a parallel ladder branchsection 16. The branch section comprises an inductor, a resistor and acapacitor. The filtered and smoothed output signal 43 from filter 33 isshown at row D in FIG. 2A.

Although the filtered data signal 43 may be Stored 0n magnetic surface30 directly by record head 27, I have found additional reliability anderror free recording is available by summing filtered signal 43 with asuitable high frequency bias signal 44 (row E, FIG. 2A) emitted by abias oscillator 34. The frequency for the output of bias oscillator 34may conveniently be several times the frequency and amplitude of theclock signal 32. For example, the oscillator bias signal 44 may beselected at a frequency that is five times greater than the frequency ofthe data signal 43.

This bias oscillator signal 44 linearizes, upon recording, the filteredsplit-phase-mark data signal 43, and thus tends to eliminate anyharmonics which may be present in the low frequency data components.These harmonics at some bit densities Within the wide capabilities ofthis invention may interfere wth the hgher frequency data at such bitdensities and could be mistaken by the demodulator as data. The use ofthe bias oscillator alone, or together with filter 33 as required,provides substantially error-free recovery of digital data over a widerange of bit densities.

As one example, the low-pass filter circuit 33 may be utilized atpacking densities such as 10,000 bits per inch. At such a packingdensity, filter 33 passes all frequencies below the bit rate which wouldin this instance be 10,000 cycles per second per inch for clock signal32. Selecting the low-pass filter with this range of low-passfrequencies eliminates the fifth harmonic from the input signal so thatit does not interfere with the bias frequency of oscillator 34 which inthe example just given would have an oscillating frequency at 50,000cycles per second. As another example, highly satisfactory operation hasbeen achieved at rates as high as 50,000 bits per second at a tape speedof two and onehalf inches per second, or a packing density of 20,000bits per linear inch. For this example the oscillator bias may be set at500,000 cycles per second. The low- .if pass filter 33 is not necessaryfor this application, and the non-filtered split-phase-mark digital datasignal 35 may be summed directly with the oscillator bias signal 44.

Head 27 applies a phase modulated envelope 45 to vention, a basictechnique of phase modulating a carrier frequency with digital datarepresented by at least two discrete levels has been described. It ispossible to double the bit density in accordance with the principles ofmy invention by utilizing a new and unique digital recording themagnetic surface 30. Although tests have not proved data format which,upon recovery, utilizes three distinct conclusively what ux patternsexist on the magnetic signal levels rather than two discrete levels asdefined surface, it is believed that the high frequency bias ofhereinbefore in connection with FIGS. 1 and 2. These envelope 45 erasesitself once it has been stored on three signal levels may be referred toas plus, minus the magnetic surface 30. This erasure is accomplished 10and zero, and exist at these levels at the output of by what is believedto be self-demagnetization of the decoder 55 through the operationdescribed hereinbeflux reversals induced at the magnetic surface 30. Thefore.

resulting flux pattern which is present on magnetic sur- To simplify theinterpretation of these three discrete face 30 between the record andthe reproduced operalevels, the input wave is coded prior to itspresentation tioins in a continually varying residual or remmnant toformat converter 25. The NRZC data to the input of fiux patternapproximately as depicted by the filtered data converter is modified inNRZ-SPACE (hereinafter modulated signal 46, FIG. 2A. NRZ-S) byadditional input circuitry for encoder 25.

During reproduce operations, this continuously vary- NRZ-S signals areformed by converting zeroes to ing residual fiux pattern induces asignal `46 into the transitions and by converting ones to notransitions. reproduce head 57 which signal includes some high fre- 20This additional encoding circuitry is added to the record quency noise.This output signal 46, as recovered, is channel 20 of my invention. Inaddition, a low-pass filter shown at row G in FIG. 2A. Recovered signal46 is and a non-zero detector is added at the output of the reamplifiedby any suitable reproduce amplifier 58 as produce channel 50 of myinvention. The simple addition known in the art, and is passed through alow-pass of these two circuits allows the employment of a clock filter53 of the type described hereinbefore. Limiter cir- 25 signal, i.e. acarrier signal which has a frequency up to cuit 59 squares the filteredsignal into its original splittwice the frequency of the availablebandwidth of the sysphase-mark form such as shown in row C of FIG. 2A.tem.

A one bit delay circuit 56 delays the filtered signal This new andunique format and the means for gen- 46 which delayed signal is alsolimited by a limiter cirerating and recovering it is describedhereinafter in concuit 60 and in its delayed and limited form, as shown30 junction with FIG. 3 and FIG. 3A. In FIG. 3 the record in row H ofFIG. 2A, is presented to a demodulator channel 20 of FIGS. 1 and 2 isreproduced in block form 60 which may be any suitable demodulator suchas a as is the reproduce channel 50 of FIGS. 1 and 2. It should doublebalanced demodulator. In FIG. 2, a double be understood that theoperation for these record and balanced demodulator 60 of conventionalform is shown reproduce channels 20 and 50 is identical to thatprecomprising a differential amplifier `63 having standard 35 viouslydescribed and thus need not be repeated with the resistive inputs to aplus and negative input side thereof. description of FIG. 3. Therecovered data modulated signal (substantially In FIG. 3A the NRZCdigital data 31 from source 21 signal of rod C, FIG. 2A) is applied tothe input is again employed as an illustration of the basic dataterminals `61 and 62 of the differential amplifier 63. format. Clocksource 22 provides a high frequency The delayed data signal 47 (row H ofFIG. 2A) is 40 carrier which may be twice the bandwidth of the recordapplied by limiter 54 to a pair of switches 64, 65, of and reproducesystem. These two input trains 31 and 32 any well known type whichrespond to opposite polarity are depicted in rows I and J of FIG. 3A. Aleading edge signals for alternately completing a circuit to grounddetector circuit receives the carrier signal 32 and an for terminals 61and 62. These switches 64, 65 are on inverter circuit 41 inverts theNRZC signal 31. An AND a mutually exclusive basis and only one switch isclosed gate 42 is connected to the output of the leading edge at any oneinstant. The following table describes a detector 40 and the invertercircuit 41 and its output is demodulating operation based upon apositive or negaapplied to a flip-fiop toggle circuit 43. The flip-fioptive level for the two input signals (substantially 35 toggle circuit 43changes state once for every input signal and signal 47) as applied todemodulator 60: and its output is applied to the format converter 25 asTABLE I Signal Input Polarity Recovered SM Signal Positive Positive.Negativa.-- Negative. Delayed SM SignaL .do Negative .do Positive.Output Signal From Demodulat-or do do Positive..- Negative.

As shown in Table l, a negative polarity signal emitted the NRZ-S signal73 shown in row K of FIG. 3. An by limiter 54, together with a negativeinput to ampli- 60 additional inverter 57 inverts the carrier signal 32and fier 63 from limiter circuit 59 results in a positive outapplies itto the format converter 25 as the carrier signal put signal which is thefirst pulse of signal train 48 74 shown in row L of FIG. 3A. Thisinverter carrier shown in row I of FIG. 2A. The negative polarity signalsignal 74 is modulated with the NRZ-S signal 73 in the from limiter 54closes switch 64 and shorts the positive format converter 25 by theoperations previously deside of amplifier 63 to ground. Thus, thenegative polar- 65 scribed in conjunction with FIGS. 1 and 2. This dataity signal from limiter 59 is applied to the negative modulated signalis again a random phase modulated terminal 62 of amplifier 63 and instandard differential wave 75 as shown in row M of FIG. 3A. As was trueamplifier operation a positive signal is emitted by amfor thedescription of FIGS. 1 and 2, the modulated data plifier 63. Switches 64and 65 continue to operate under may be filtered and biased prior torecording by head control and in accordance with the polarity of thesignal 27 on the magnetic surface 30. A reproduce head 57 emitted bylimiter circuit 54. Differential amplifier 63, recovers the modulatedNRZ-S data, in the manner dein accordance with the polarity of the inputsignal scribed hereinbefore, is again delayed (signal 76, row emttedfrom limiter circuit 59, responds to its grounded N, FIG. 3A) anddemodulated so as to reconstruct the input conditions by emitting signal48, FIG. 2A. NRZ-S data wave train 78 shown in row 0 of FIG. 3A.

In accordance with the foregoing operation of my in- Comparison of FIG.3A to FIG. 2A shows a `bit cell that appears to be the same width foreach of the pulse wave form charts. It should be understood, however,that the frequency r bit repetition rate of FIG. 3A may be twice thefrequency and bit rate of the'pulse wave form chart of FIGS. lA and 2A.Thus, the bit cells of FIG. 3A are in actual operation extremely narrowin time duration and represent a frequency which may be as high as twicethe upper frequency of the available bandwidth of the system. It isobvious, of course, that any system has a gradual transition frommaximum to zero transmittence and does not have an absolute upper cutofffrequency. However, at some signal-to-noise ratio such as, for example,18 to 20 decibels, a given system may be considered as having reachedits upper frequency limit. If this upper frequency limit is referred toas f1, then the maximum bit density for the system of FIG. 3 may bedefined as 211.

When operating at 2f1, the decoder 55 of FIGS. 1 and 2 tries to changefrom a plus to a minus or from a minus to a plus but does not have timeto reach either level before it is demodulating another digital valve.This decoder 55, rather than emitting an NRZ-S signal 78 of row 0, FIG.3A, emits instead a continuously varying signal substantially like thatof signal 82 shown in row P of FIG. 3A. Signal 82 is restored to an NRZCformat by a ternary data detector circuit 80.

This ternary data detector circuit 80 includes a lowpass filter circuit81 which is selected to pass frequencies up to f1. Connected to theoutput of filter 81 is a positive threshold detector circuit 83 and anegative threshold detector circuit 84. An OR gate 86 is connected tothe outputs of detectors 83 and 84. As shown in FIG. 3A by a comparisonof the signals shown in rows P and Q, either detector 83 or detector 84emits an output indication to OR gate 86 whenever the input signal 82 isnot zero. Thus, whenever input signal 82 is greater or less than thezero level shown between the two dashed horizontal lines, an outputlevel of one is presented at OR gate 86. These dashed lines, in standarddetector operation, represent the threshold values for detectors 83 and84. A zero output is presented at OR gate 86 whenever signal 82 iswithin these voltage levels shown as dashed lines. Thus, the not Zerodetector 80 restores signal 82 to an NRZC data format at bit rates whichare twice as high as the upper cut-off frequency of the bandwith of thesystem.

Although all prior descriptions of this invention have referred toone-track data handling capability, it should be understood that aplurality of data tracks may be provided for. Furthermore, it should beunderstood that more than one data train, or channel, could be handledby employing the principles of this invention in a phase multiplexedoperation. Thus, rather than using a phase shift of 180 for one datachannel, two or more data channels may be provided with phase shifts of0 to 90 and 90 to 180 and both (or more) channels would be delayed onebit interval, and thereafter phase separated in order to recover bothseparate data channels.

It is to be understood that the foregoing features and principles ofthis invention are merely descriptive, and that many departures andvariations thereof are possible by those skilled in the art, withoutdeparting from the spirit and scope of this invention.

What is claimed is:

1. In a method of high density recording of data on a magnetic mediumwherein the data is represented as one or the other of two levels in aplurality of bit cells, the steps comprising modulating a constantfrequency signal with the two levels so as to represent one data levelin the modulated signal as one distinct recurring frequency within eachbit cell, and the other data level as a second distinct recurringfrequency within a bit cell, applying the modulated signal to a magneticmedium at an amplitude less than a saturation amplitude for the magneticmedium,

recovering the modulated signal from the magnetic medium, and

delaying the modulated signal by one bit cell or a fixed multiplethereof,

comparing the phase of the modulated signal with the phase of thedelayed signal, and

representing phase similarities as one data level and phase variationsas the other data level.

2. In a data handling method in accordance with claim 1 the additionalsteps comprising:

performing the comparison step continually during individual comparisontimes equal to bit cell intervals in order to represent phasesimilarities appearing over a comparison time as one data level, and torepresent phase variations appearing over a comparison time as the otherdata level.

3. A method of transferring high density data relative to a magneticmedium in which the data includes binary bits represented by a pluralityof discrete levels appearing for assigned durations during bit cellintervals, the steps comprising:

representing each data bit cell by at least one cycle of a square-wavecarrier clock signal;

modulating the carrier clock signal with the discrete data levels toobtain a continuous square-wave signal in which the discrete data levelsare represented as guaranteed level transitions between adjacent bitcells with one-bit type assigned an additional transition at each midbitcell time of the bit cells occupied by said one-bit type;

low-pass filtering the continuous data-representing signal to acorresponding continuous analog signal in which said one-bit type isrepresented as one cycle in a bit cell and continues into another cycleor continues into one-half of a cycle in an adjoining bit cell dependingupon storage of said one or other bit types respectively; and

recording the bit-representing analog signal as continuous iiuxvariations on a magnetic medium.

4. A method of data handling for a magnetic storage medium in accordancewith claim 3 and further comprising the steps of:

converting the continuous iiux variations to a detected signal;

delaying the detected signal by at least one bit cell duration; andlow-pass filtering the modulated signal to provide an analog signalhaving one complete cycle in a bit cell representing said one-bit type,said analog signal continuing into either another cycle or continuinginto a half-cycle in an adjoining bit cell for respectively representingsaid one or said other bit types; and

nonsaturably recording the data modulated low-pass filtered signal ascontinuous ux variations on a magnetic medium.

5. In a method for recording bits of data on a magnetic medium whereinthe data for each bit cell is represented as one or the other of twodiscrete levels extending for the duration of a bit cell the stepscomprising:

selecting the frequency of a clock signal t0 have at least one cyclesynchronized with each bit cell; modulating the clock signal with thetwo discrete levels so as to represent binary data as a continuoussignal in which lbinary bits of both types include a level transition atbit boundaries with one bit type further represented by a transitionfrom one level to the other level substantially at the middle of a bitcell and the other bit type is further represented by the lack of atransition at the middle of a bit delayed version of the signal isadapted for comparison with itself during decoding to automaticallyyield the original discrete data level free of any decoding clock; alow-pass filter connected to said format control means for convertingsaid continuous signal therefrom to an analog signal wherein saidone-bit type is represented by a full cycle within a bit cell, whichfull cycle in an adjoining bit cell continues into another full cyclefor said one-bit value or continues into one-half a cycle for the otherbit value;

a bias means for linearizing the continuous analog signal passed fromthe low-pass filter; and

a signal responsive transducer means connected to said bias means andoperatively coupled to a magnetic medium for recording said continuousanalog signal as a continuous ux variation thereon.

6. A method of recovering bits of data recorded on a magnetic medium inaccordance With claim 5, comprising the steps of:

recovering a signal from the nonsaturated flux variations representingthe modulated signal from the magnetic medium; and

demodulating the recovered signal free of any recovery clock bycomparing it with a one-bit delayed version of itself so as to convert amidbit transition to the other discrete data level. 7. Apparatus fortransferring, relative to a magnetic medium, data appearing for assignedbit cell intervals in which bits of one type are a irst data level andbits of a second type are a second data level, the apparatus comprising:

means for receiving from a magnetic storage medium a continuous signalhaving guaranteed level transitions at each bit cell boundary with ibitsof one type represented by an additional midbit level transition andbits of another type represented by the lack of an additional midbittransition; delay means connected to said signal receiving means fordelaying the received signal one bit cell interval or a whole multiplethereof; and

signal decoding means connected to compare said delayed signal and saidreceived signal and operative in response to a comparison between thetwo signals for emitting one data level during the duration that phasesof the compared signals are identical and for emitting the other datalevel during the duration that phases of the compared signals areopposite.

8. Apparatus for transferring data in accordance with claim 7 whereinthe format of the continuous signal is such that a one bit delayedversion of itself compares with like phases for durations substantiallyequal to a bit cell interval and/or compares with opposite phases fordurations substantially equal to a bit cell interval and wherein:

said signal decoding means is continually operative during saidcomparison durations to automatically emit one data level for likephases and another data level for opposite phases in the comparedsignal. 9. Apparatus for transferring data in accordance with claim 7wherein:

the received signal is an analog signal and said delay means is ananalog signal delay circuit -for emitting a delayed analog signal andfurther comprising signal limiting means connected to receive saiddelayed analog signal and said received analog signal for convertingsaid analog signals to corresponding square-Wave signals; and

means connecting the square wave signals emitted from said limitingmeans to said signal decoding means.

10. Apparatus for transferring, relative to a magnetic medium dataappearing for assigned bit cell intervals in which bits of one type area first level and bits of a second type are a second level, theapparatus comprising:

means for emitting a continuous signal having guaranteed leveltransitions at each bit cell boundary with bits of one type representedby an additional midbit level transition and bits of another typerepresented by the lack of an additional midbit transition such that aone-bit delayed version of the signal is adapted for comparison withitself during decoding to yield the original discrete data levels;

means connected to said signal emitting means for recording saiddata-containing signal as continuous ilux variations on a magneticmedium;

means for recovering from said magnetic storage medium a continuoussignal derived from the continuous flux variations and having guaranteedlevel transitions at each bit cell boundary with bits of one typerepresented by an additional midbit level transition and bits of anothertype represented 'by the lack of an additional midbit transition;

delay means connected to said signal receiving means for delaying thereceived signal one-bit cell interval or a whole multiple thereof; and

signal comparing means connected to receive said delayed signal and saidrecovered signal and o-perative free of any clocking signal for emittinga first level when the compared signals are the same and for emitting asecond level when the compared signals are different.

11. Apparatus for transferring, relative to a magnetic medium dataappearing for assigned bit cell intervals in which bits of one type area rst level and bits of a second type are a second level, the apparatuscomprising: f

means for receiving from a magnetic storage medium a continuous signalhaving guaranteed level transitions at each bit cell |boundary with bitsof one type represented by an additional midbit level transition andbits of another type represented by the lack of an additional midbittransition;

delay means connected to said signal receiving means for delaying thereceived signal one-bit cell interval or a whole multiple thereof; and

signal comparing means connected to receive said delayed signal and saidreceived signal and operative in response thereto free of any clockingsignal for emitting said rst level when the compared signals are thesame for emitting said second level when the compared signals aredifferent.

12. Apparatus for transferring data in accordance with claim 11 wherein:

said signal comparing means continually emits one level for one bit typeduring a bit cell interval that the compared signals are the same, andcontinually emits another level for the other bit type during a bit cellinterval that the compared signals are different.

13. Apparatus for transferring data in accordance with claim 11 wherein:

the received signal is an analog signal and said delay means is ananalog signal delay circuit for emitting a delayed analog signal.

14. Apparatus for transferring data in accordance with claim 13 andfurther comprising:

signal limiting means connected to receive said delayed analog signaland said received analog signal for converting said analog signals tocorresponding continuous square-wave signals; and

means connecting the square wave signals emitted from said limitingmeans to said signal comparing means.

15. A system Vfor recording data on a magnetic medium wherein binarydata or two-bit types is provided to the system in at least two discretelevels extending for predetermined duration of data Ibit cells, saidsystem comprising:

means for emitting a square-wave clock signal having a frequency whichprovides one signal synchronized with each bit cell;

format control means connected to said clock signal emitting means andadapted to receive said data for converting said clock signal and saiddata levels to a continuous signal which includes a level transitionsubstantially at the beginning of every bit cell for both of said bittypes and further including a level transition substantially at midbittime of each bit cell which includes one only of said bit types, suchthat a one-bit combining the detected and delayed signals togetherwhereby the plurality of discrete levels representing the data arerestored free of any decoding clock signal.

16. A system in accordance with claim 15 wherein said format controlmeans further comprises:

means connecting said filter means between said format control means andthe bias means for smoothing out the levels and level transitionsgenerated thereby to said analog signal wave.

17. A system in accordance with claim 16 wherein said system has a broad`bandwidth including an upper frequency limit and wherein said clocksignal emitting means has a frequency selected from within saidbandwidth, and

wherein said filter means is a pass filter operative for passingfrequencies below said upper frequency limit.

18. A system in accordance with claim 17 and further comprising meansconnecting said filter means to said transducer means.

19. A system in accordance with claim 18 wherein said connecting meanscomprises a signal summing junction, and wherein said bias means furthercomprises an oscillator for emitting a bias signal having a frequencygreater than said upper frequency limit, and

means connecting said oscillator to said signal summing junction forsumming directly said iiltered signal and said lbias signal.

20. A system in accordance with claim 15 and further comprising meansfor reproducing said data stored on said medium, said reproducing meanscomprising a second signal responsive transducer operatively coupled tosaid magnetic medium and responsive to relative movement therebetweenfor recovering said flux variations, and

demodulating means connected to said second transducer for extractingfrom said carrier signal said different data levels.

21. A system in accordance with claim 20 wherein said demodulating meanscomprises a delay circuit connected to said second transducer,

said circuit having a delay time equal to, or a multiple of, a bit cellduration,

a phase comparison circuit having lirst and second inputs respectivelyconnected to said delay circuit and to said second transducer means, and

means including said phase comparison circuit for emitting one outputlevel for similarity in the phases of said signals applied thereto and asecond different output level for variations in the phases of saidsignals applied thereto.

References Cited UNITED STATES PATENTS 1/1966 Hopner S40-174.1 12/ 1967Halfhill et al 340-1741 10/ 1968 Halfhill et al 340-1741 Us. C1. X.R.

UNITED STATES PATENT OFFICE CERTIFICATE OF CORRECTION Patent No.3,518,648 June 3U, 1970 Kermit A. Norris It is certified that errorappears in the above identified patent and that said Letters Patent arehereby corrected as shown below:

Column 3, line 2l, "decibals should read decibels line 30, "priciples"should read principles line 47, "of duration' should read or durationColumn 6, line l4, "Recordingly" should read Accordingly line 54, "wththe hgher" should read with the higher Column 7, line l4, "reproduced"should read reproduce g lines 14 and l5, "operatioins" should readoperations line l5, "remmnant" should read remnantF same line l5, "in"should read is line 38, "rod" should read row --3 line 73, "emtted"should read emitted Column 8, line 62, "inverter'I should read invertedColumn 9, line Z2, "valve" should read value Column l0, lines 49 through57 should be cancel and the following inserted:

combining the detected and delayed signals together whereby theplurality of discrete levels representing the data are restored free ofany decoding clock signal.

same column l0, line 7l, starting with "delayed version" through line75, should be camceled. Column ll, lines l through l2, should becanceled and the following inserted:

cell; lowpass filtering the modulated signal to provide an analog signalhaving one complete cycle in a bit cell representing said one-bit type,said analog signal continuing into either another cycle or continuinginto a half-cycle in an adjoining bit cell for respectively representingsaid one or said other bit types; and

nonsaturably recording the data modulated low-pass filtered signal ascontinuous flux variations on a magnetic medium. Column l2, line 39,after "same" insert and Column 13, lines through 6 should be canceledand the following inserted:

delayed versions of the signal is adapted for comparison with itselfduring decoding to automatically yield the original discrete data levelfree of any decoding clock;

a low`pass filter connected to said format control meams for convertingsaid continuous signal therefrom to an analog signal wherein saidone-bit type is represented by a full cycle within a bit cell, whichfull cycle in an adjoining bit cell continues into another full cyclefor said one-bit Value or continues into one-half a cycle for the otherbit Value;

a bias means for linearizing the continuous analog signal passed fromthe low-pass filter; and

a signal responsive transducer means connected to said bias means andoperatively coupled to a magnetic medium for recording said continuousanalog signal as a continuous flux variation thereon.

Signed and sealed this 23rd day of February l97l.

(SEAL) Attest:

EDWARD M. FLETCHER,JR. WILLIAM E. SCHUYLER, JR.

Attesting Officer Commissioner of Patents

